Adaptation JTAG Debugger for QorIQ PowerPC 32/64 Bit (ICD)

Connector 16 pin

Signal	Pin			Pin	Signal
TDO	1			2	N/C
TDI	3			4	TRST-
(RUNSTOP-)	5			6	JTAG-VREF
TCK	7			8	(CHKSTPIN-)
TMS	9			10	N/C
(SRESET-)	11			12	GND
PORESET-	13			14	N/C (KEY PIN)
(CKSTOPOUT-)	15			16	GND

• Signals driven by the debug probe: TDI, TCK, TMS, PORESET- (open-drain), TRST-, CHKSTPIN-. These signals habe a built-in 47 Ohm serial termination.
• Signals that are an input to the dbeug probe: TDO, RUNSTOP-, SRESET-, CKSTOPOUT-, JTAG-VTREF. These signals have a 10 Ohm serial termination.
• Pin 6 (JTAG-VREF) must match the JTAG I/O voltage of the processor. JTAG-VREF should have a resistance less than 5kOhm for 3.0~5.0V, less than 2kOhm for 1.8~3.0V.
• Pin 8 will, by default, be permanently driven to VCC level by the debugger.
• Signals in brackets are not necessary for debugging, but it is recommended to connect those signals if available.
• Signals which are not available should be left unconnected on the debug connector.

Dimension

Connector Type

• This is a standard 16 pin double row (two rows of 8 pins) connector (pin to pin spacing: 2.54mm/0.100").
• If terminal strip without shroud is used, the spacing marked with "A" must be a minimum of 25.5mm/1".
• Examples with housing: Samtec HTST-108-01-L-D (through-hole); Samtec HTST-108-01-L-DV (surface mount).

	Half-Size Adapters for Debuggers 100 mil to 50 mil Adapters Small Footprint for Target Connector