MIPI20T Connector for Debug and Trace
|
Signal
| Pin
| | Pin
| Signal
|
| | | | |
VREF-DEBUG | 1 | | | 2 | TMS|TMSC|SWDIO |
GND | 3 | | | 4 | TCK|TCKC|SWCLK |
GND | 5 | | | 6 | TDO|-|SWO |
GND (KEY) | 7 | | | 8 | TDI |
GND | 9 | | | 10 | RESET- |
GND | 11 | | | 12 | TRACECLK |
GND | 13 | | | 14 | TRACEDATA[0] |
GND | 15 | | | 16 | TRACEDATA[1] |
GND | 17 | | | 18 | TRACEDATA[2] |
GND | 19 | | | 20 | TRACEDATA[3] |
| | | | |
Note:
Off-chip tracing is only supported by µTrace® for Cortex-M.
However, µTrace® for RISC-V will support off-chip trace promptly after adoption of a trace standard by the RISC-V Foundation.
MIPI10 Connector for Debug Only (with optional Serial Wire Output)
|
Signal
| Pin
| | Pin
| Signal
|
| | | | |
VREF-DEBUG | 1 | | | 2 | TMS|TMSC|SWDIO |
GND | 3 | | | 4 | TCK|TCKC|SWCLK |
GND | 5 | | | 6 | TDO|-|SWO |
GND (KEY) | 7 | | | 8 | TDI |
GND | 9 | | | 10 | RESET- |
| | | | |
IDC20A Connector for Debug Only (with opt. Serial Wire Output) via Included Converter LA-2730
|
Signal
| Pin
| | Pin
| Signal
|
| | | | |
VREF-DEBUG | 1 | | | 2 | VSUPPLY (not used) |
TRST- | 3 | | | 4 | GND |
TDI | 5 | | | 6 | GND |
TMS|TMSC|SWDIO | 7 | | | 8 | GND |
TCK|TCKC|SWCLK | 9 | | | 10 | GND |
N/C | 11 | | | 12 | GND |
TDO | 13 | | | 14 | GND |
RESET- | 15 | | | 16 | GND |
N/C | 17 | | | 18 | GND |
N/C | 19 | | | 20 | GND |
| | | | |
Pin |
Direction |
Description |
TCK|TCKC|SWCLK |
to CPU |
JTAG Clock. It is recommended to put a pull-down to GND on this signal. |
TMS |
to CPU |
Standard JTAG TMS: It is recommended to put a pull-up to VTREF on this signal for standard 4-pin JTAG. |
TMSC |
to/from CPU |
Compact JTAG TMSC: Your chip should have a bus-hold on this line for compact JTAG. |
SWDIO |
to/from CPU |
Serial Wire Debug In/Out |
TDI |
to CPU |
JTAG TDI. It is recommended to put a pull-up to VTREF on this signal.
Only required for standard 4-pin JTAG / Optional signal for compact JTAG.
|
TDO |
from CPU |
JTAG TDO. (No pull-up or pull-down is required.)
Only required for standard 4-pin JTAG / Optional signal for compact JTAG.
|
VREF-DEBUG |
from CPU |
Reference voltage. This voltage should indicate the nominal HIGH level for the debug and trace pins.
So for example, if your signals have a voltage swing from 0 V ... 3.3 V, the VTREF pin should be connected to 3.3 V.
|
RESET- |
to/from CPU |
System Reset Signal. (Optional)
If your target board has a low active CPU reset signal, you can
connect this low active reset signal to this pin.
This enables the debugger to detect a CPU reset.
Furthermore the debugger can drive this pin to GND to hold the CPU in
the reset state. The debugger drives this pin as open-drain,
so a pull-up is mandatory.
|
TRC CLK |
from CPU |
Trace clock (used with off-chip trace) |
TRC DATA[3..0] |
from CPU |
Trace data (used with off-chip trace) |
The MIPI20T-HS Whisker of a µTrace ® can be used directly with two different connectors (MIPI10, MIPI20T).
Via the includes converter LA-2730,
the MIPI20T-HS Whisker can be connected to a classic IDC20A debug connector, too.
µTrace ® supports various interface standards:
JTAG | IEEE 1149.1 | alternate pin function: TMS, TCK, TDO |
Compact JTAG | IEEE 1149.7 | alternate pin function: TMSC, TCKC, - |
Serial Wire Debug | CoreSight ARM | alternate pin function: SWDIO, SWCLK, SWO |
Interface type and corresponding pin function can be selected in the debugger GUI.
To connect to a target with a different connector, the following converters can be used.
The converter LA-2730 to connect to a classic IDC20A debug connector, is already included in your µTrace ® package.
Converter MIPI-20T to IDC20A
Converter MIPI-20T to MIPI-34
Converter MIPI-20T to MICTOR-38
Converter MIPI-20T to TI-14
|