Pinout Specification IDC20A Debug Cable

Arm compatible 20-pin IDC connector with pins on 0.100" centers

Signal	Pin			Pin	Signal
VREF-DEBUG	1			2	VSUPPLY (not used)
TRST-	3			4	GND
TDI	5			6	GND
TMS|TMSC|SWDIO	7			8	GND
TCK|TCKC|SWCLK	9			10	GND
RTCK	11			12	GND
TDO|-|SWO	13			14	GND
RESET-	15			16	GND
DBGRQ	17			18	GND
DBGACK	19			20	GND
Target connector, top-view

Pin	Direction	Description
TCK|TCKC|SWCLK	to CPU	JTAG Clock. It is recommended to put a pull-down to GND on this signal.
TMS	to CPU	Standard JTAG TMS. It is recommended to put a pull-up to VTREF on this signal for standard 4-pin JTAG.
TMSC	to/from CPU	Compact JTAG TMSC. Your chip should have a bus-hold on this line for compact JTAG.
SWDIO	to/from CPU	Serial Wire Debug In/Out
TDI	to CPU	JTAG TDI. It is recommended to put a pull-up to VTREF on this signal. Only required for standard 4-pin JTAG, optional signal for compact JTAG.
TDO	from CPU	JTAG TDO. No pull-up or pull-down is required. Only required for standard 4-pin JTAG, optional signal for compact JTAG.
TRST-	to CPU	JTAG Test Reset (optional). This is an active low signal. A pull-up on the target is recommended.
RTCK	from CPU	JTAG Return Clock (optional). Available for Arm and a few other architectures. No pull-up or pull-down is required. Leave open (N/C) if not used.
VREF-DEBUG	from CPU	Reference voltage. This voltage should indicate the nominal HIGH level the for the debug signals (JTAG, cJTAG, SWD). So for example, if your signals have a voltage swing from 0 V ... 3.3 V, the VTREF pin should be connected to 3.3 V.
VSUPPLY	from CPU	Voltage supply. LAUTERBACH debug probes have their own dedicated power supply. As such, this line is not utilized.
GND	to/from CPU	Ground. Connect all GND pins to minimize noise interference.
RESET-	to/from CPU	System Reset (optional). If your target board has a low active CPU reset signal, you can connect this low active reset signal to this pin. This enables the debugger to detect a CPU reset. Furthermore the debugger can drive this pin to GND to hold the CPU in the reset state. The debugger drives this pin as open-drain, so a pull-up is mandatory.
DBGRQ	to CPU	Debug Request (optional, Arm architecture only). Used with some Arm-based chips to stop all Arm cores. Leave open (N/C) if not used.
DBGACK	from CPU	Debug Acknowledge (optional, Arm architecture only). Indicates on some Arm-based chips, if the Arm cores are running. Leave open (N/C) if not used.
EVTI (17)	to CPU	Nexus Event In (optional, ARC architecture only). Only used with DesignWare ARC Trace to force a Nexus Synchronization Message.
EVTO (19)	from CPU	Nexus Event Out (optional, ARC architecture only). This pin is not used by ARC processors. Leave open (N/C) if not used.

The Debug Cable supports different interface standards:

1	JTAG	IEEE 1149.1	alternate pin function: TMS, TCK
3	Compact JTAG	IEEE 1149.7	alternate pin function: TMSC, TCKC
2	Serial Wire Debug	CoreSight Arm®	alternate pin function: SWDIO, SWCLK

The interface type and corresponding pin function can be selected in the debuggers GUI.

For board designs requiring a smaller debug connector footprint we recommend to use a 20-pin or 10-pin MIPI connector via one of the following converters:

LA-2729 Converter IDC20A to MIPI-10/20T (Recommended, since easy and robust)
LA-3770 Converter IDC20A to MIPI-10/20D/34 (Use only if you need legacy debug signals RTCK, DBGRQ, DBGACK, TRST-)

Learn more about the differences between the two converters in the Lauterbach knowledge base.